1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and to a semiconductor device, particularly to a MOS (Metal Oxide Semiconductor) type field effect transistor.
2. Description of the Related Art
In recent years, for obtaining enhanced transistor performance, investigations have been made of application of a stress to a channel region so as to increase the drain current. As a technique of applying a stress, a method has been reported in which after the formation of a gate electrode, a film having a high stress is formed so as to apply a stress to the channel region. Also, a method has been reported in which the source/drain regions of a P-channel MOS type field effect transistor (PMOSFET) are etched, and a silicon-germanium (SiGe) layer is epitaxially grown in the etched portion so as to apply a stress to the channel region (refer to, for example, JP-A-2002-530864 (refer, particularly, to FIG. 4 and Paragraph No. 0030)). The application of a stress to the channel region by use of the SiGe layer is more effective as the SiGe layer is nearer to the channel region and as the volume of the SiGe layer is greater.
Here, a method of manufacturing the PMOSFET as above-mentioned will be described referring to FIGS. 3A to 3G. First, as shown in FIG. 3A, device isolation regions (omitted in the figure) are formed on the face side of a silicon substrate 11. Next, a gate electrode 13 including polysilicon is patternedly formed over the silicon substrate 11, with a gate insulation film 12 including silicon oxide therebetween. In this case, materials constituting the gate insulation film 12 and the gate electrode 13 and a hard mask 14 including a silicon nitride film are stackedly formed over the silicon substrate 11, and the stacked films are patterned by etching.
Next, as shown in FIG. 3B, a silicon nitride film 15′ is formed over the silicon substrate 11 in the state of covering the gate insulation film 12, the gate electrode 13 and the hard mask 14. Thereafter, as shown in FIG. 3C, the silicon nitride film 15′ (see FIG. 3B) is etched back by a dry etching method, to form side walls 15 on both sides of the gate insulation film 12, the gate electrode 13 and the hard mask 14.
Subsequently, as shown in FIG. 3D, by using the hard mask 14 and the side walls 15 as a mask, the so-called recess etching which includes digging down the silicon substrate 11 is conducted, to form recess regions 16. Thereafter, by a cleaning treatment using diluted hydrofluoric acid, a natural oxide film on the surface of the substrate is removed.
Next, as shown in FIG. 3E, a silicon-germanium (SiGe) layer 17 is epitaxially grown on the surfaces of the recessed regions 16, i.e., on the dug-down surfaces of the silicon substrate 11. This results in formation of an SiGe layer 17 containing Ge in a predetermined concentration. Thereafter, a p-type impurity is introduced into the SiGe layer 17 by an ion implantation method, and activating anneal is conducted. As a result, the SiGe layer 17 constitutes source/drain regions, and the region, located beneath the gate electrode 13 and located between the source/drain regions, of the silicon substrate 11 becomes a channel region Ch.
Next, as shown in FIG. 3F, the hard mask 14 (see FIG. 3E) is removed by wet etching in which hot phosphoric acid is used, whereby the surface of the gate electrode 13 is exposed, and the natural oxide film on the surface of the SiGe layer 17 is removed. By this removing step, upper parts of the side walls 15 are also removed.
Subsequently, as shown in FIG. 3G, a high melting point metal film such as a nickel film is formed over the silicon substrate 11, inclusive of the areas on the SiGe layer 17, in the state of covering the gate electrode 13. Thereafter, a heat treatment is conducted, whereby the surface side of the gate electrode 13 and the surface side of the SiGe layer 17 are silicided, to form a silicide layer S including nickel silicide. As a result, the resistance on the surface side of the source/drain regions is lowered, and a lowered contact resistance is realized.
When the channel region Ch is strained by application of a stress thereto by the SiGe layer 17 as above-mentioned, a PMOSFET having a sufficient carrier mobility can be obtained.